CSG1300 CPLD Upgrade : Versa Support

CPLD Upgrade Procedure

1. Before upgrading CPLD, please check and make sure BIOS version is the latest compatible version with the CPLD.

[admin@Perf-Branch3: ~] $ sudo dmidecode -t 0

Handle 0x0000, DMI type 0, 24 bytes

BIOS Information

Vendor: American Megatrends Inc.

Version: v46.01.05.00

Release Date: 06/23/2021

CPLD version CSG1300_DNV_CPU_V40.jbc requires BIOS version CSG1300_bios_v46.01.05.00.bin

Please refer to BIOS upgrade procedure:

https://support.versa-networks.com/a/solutions/articles/23000023295

Note: system does not need to be power-cycled after BIOS upgrade if CPLD is going to be upgraded immediately. System needs to be power-cycled after CPLD upgrade for the new BIOS and CPLD to take effect.

2. Download and the extract the latest CPLD files from below link required for upgrade procedure

CPU CPLD Versa 4.2

CSG1300_DNV_CPLD_V42.jbc

https://versanetworks.box.com/s/8o7pbmsn2ykd6d1c2oyfcd0nx7gleux0

3. Copy below files to DUT into /var/tmp directory

cpldupd
cpldutil
CSG1300_DNV_CPU_Vxx.jbc

4. Verify the CPLD version once before upgrade as shown below

Method 1 to check CPLD version: (supported in ALL VOS releases)

[admin@versa-flexvnf: ~] $ sudo i2cdetect -l

i2c-0 smbus SMBus iSMT adapter at dffba000 SMBus adapter <<<< iSMT is on i2c bus 0

i2c-1 smbus SMBus I801 adapter at e000 SMBus adapter

[admin@versa-flexvnf: ~] $ sudo i2cget -y 0 0x65 1 <<< i2c bus corresponding to iSMT in the above command

0x42 <<<<<<< CPLD version

Method 2 to check CPLD version:

Note: Command shown below, "vsm-vcsn0> show chassis cpld info cpu," is ONLY supported in VOS 21.1.3 or higher. This command is NOT SUPPORTED in VOS 21.1.2 or lower.

vsh connect vsmd
show chassis cpld info cpu
exit
CPU CPLD is highlighted in yellow

vsm-vcsn0> show chassis cpld info cpu

CPU CPLD Registers

--------------------------------------

BOARD Info (0x00) : 0a

CPLD Version (0x01) : 32

System State Control (0x20) : 0f

Reset Device 1 (0x21) : 7f

Reset Device 2 (0x22) : 07

Reset Device 3 (0x23) : 01

Interrupt State (0x30) : 08

Interrupt IF (0x31) : 18

Interrupt Mask (0x32) : 07

Watchdog Timer target (0x35) : cc

Watchdog Timer ev record (0x36) : cc

Watchdog Timer enable (0x37) : cc

Watchdog Timer count (0x38) : cc

Thermal Status (0x41) : 1f

USB Protec (0x44) : 03

PEX8714 status (0x45) : 03

5. Assign cpldupd and cpldutil binaries executable permission from /var/tmp directory

sudo chmod +x cpldupd
sudo chmod +x cpldutil

6. Stop Versa services with following command

vsh stop

7. Execute following command to upgrade the CPLD on the system

sudo ./cpldupd -u CPU_DNV CSG1300_DNV_CPU_Vxx.jbc
Upon successful completion of upgrade below output should be seen

[admin@SDWAN-Branch1: ~] $ sudo ./cpldupd -u CPU_DNV CSG1300_DNV_CPLD_V42.jbc

=== CPU_DNV CSG1300_DNV_CPU_V40.jbc ===

4A 41 4D 01 00 00 00 44 00 00 00 8C 00 00 02 E2

00 00 10 1D 00 00 11 72 00 00 11 E2 00 00 21 C7

00 01 66 61 00 01 D9 29 00 01 D9 29 00 00 07 D6

Update CPLD code from memory buffer 0x25618b0, filesize=0x1D92B

CFG.TCK_SETUP=0

CFG.TCK_HOLD=0

CFG.DO_DISABLE_ISP_CLAMP=1

CFG.DO_REAL_TIME_ISP=1

CFG.DO_FORCE_SRAM_DOWNLOAD=0

Expected CRC: 0xCD0A

Calculated CRC: 0xCD0A

SIDEBAND BASE ADDRESS = 880000000

-->

Device #1 IDCODE is 0310A0DD

Warning: ignore CFM1 flag

Check Max 10 FPGA backup data ...

erasing Max 10 FPGA CFM0 block at sector 4 ...

erasing Max 10 FPGA CFM0 block at sector 5 ...

programming Max 10 FPGA CFM0 block at sector 4 ...

programming Max 10 FPGA CFM0 block at sector 5 ...

verifying Max 10 FPGA CFM0 block at sector 4 ...

verifying Max 10 FPGA CFM0 block at sector 5 ...

DONE

<--

Clock Count=4271739

Function returned success

exec_result: 0, exit code: 0; file format version: 2

spend_time=94s

[admin@SDWAN-Branch1: ~] $

8. Once Upgrade procedure is completed, powercycle the system (unplug the power cords, wait for 10 seconds and plug them back in)

9. Verify the CPLD version after powercycleing the system